PCB Trace Width, Resistance & Temperature Calculator
IPC-2221 compliant trace width calculation with resistance, voltage drop, power dissipation, temperature rise and practical design suggestions.
Disclaimer: Based on IPC-2221 standard formulas for estimation purposes. Real-world results depend on PCB manufacturer tolerances, copper purity, surface finish and thermal environment. Always verify with your PCB design tool and manufacturer. Dr Darla accepts no responsibility for design decisions based on this tool.
Layer & Current
RMS current (A)
= 35 µm = 1.378 mils copper thickness
Trace Geometry & Temperature
= 3,937 mils
mm
= 78.7 mils
Leave as-is or enter your design value
IPC typical: 10 degC external, 20 degC internal
Min Width (IPC)
--
mm
Trace Resistance
--
m ohm
Voltage Drop
--
mV
Power Loss
--
mW
Temp Rise (actual)
--
degC
Operating Temp
--
degC
Fusing Current
--
A (Onderdonk)
Vdrop %
--
% of supply
Trace Width Comparison
Resistance vs Temperature
Copper resistivity increases with temperature: R(T) = R20 x (1 + 0.00393 x (T - 20))
IPC-2221 Formula Working
Design Suggestions
Full Parameter Table
Via Specification
Select a standard via size or enter custom dimensions. Results follow IPC-2221 via current capacity guidelines.
Common via sizes (click to select)
Typically drill + 0.25-0.3mm annular ring
Standard: 1.0mm, 1.6mm, 2.0mm
Via Resistance
--
m-Ohm each
Max current (1 via)
--
A
Parallel capacity
--
A total
Vias needed for I
--
vias minimum
Via Detail
Via Rules of Thumb
⬤
Plating is the bottleneck
Via barrel plating (18-25um) is thinner than trace copper (35um for 1oz). The via, not the trace, often limits current on 1oz boards.
⚡
Always use multiple vias
For currents above 1A, use 2+ vias in parallel. Derating applies: 2 vias carry about 1.8x, not 2x, due to manufacturing variation.
⚓
Via-in-pad for high current
Filled and capped via-in-pad maximises current density at component pads. Requires filled via process — specify to your PCB fab.
⚙
Thermal vias for heat spreading
Add thermal vias under power pads (e.g. exposed pad QFN) in a grid pattern. Typical: 0.3mm drill, 0.5mm pad, 1mm pitch grid.
⚠ Critical Rules — Always Apply
📏
Never use the IPC minimum as your design width
IPC-2221 minimum is an absolute floor. PCB manufacturers have tolerances of +/-0.05 to 0.1mm. Always add at least 20% margin above the calculated minimum. For production boards, add 30%.
Design width = IPC_min x 1.2 (min) to x 1.3 (production)
△
Never use 90-degree corners on power traces
Sharp 90-degree inner corners create acid traps during etching, thinning the copper at the bend. Use 45-degree chamfers or curved bends (radius >= trace width). This also reduces EMI radiation from high-frequency switching.
Minimum bend radius = 3 x trace width
🔥
Never neck down at IC pads without re-widening
A trace that narrows at a component pad forces all current through the restriction. The narrow section is the hottest point and the first to fail. Keep trace width consistent to the pad or use teardrops.
Use teardrops at pad junctions for reliability
⚡
Internal layer traces need wider width for same current
IPC-2221 uses k=0.024 for internal layers vs k=0.048 for external. Internal traces have no convective cooling from air. For the same current and temperature rise, internal traces must be approximately 2x wider than external.
Internal width ≈ External width x 2.0 for same temperature rise
⏳ Temperature Zone Guidelines
🏠
Consumer electronics: ΔT ≤ 10°C above ambient
Products used indoors at 25°C ambient. IPC-2221 default. Board temperature stays manageable and component reliability is maintained. If ambient can reach 40°C, design for operating temp ≤ 50°C.
Target: ΔT = 10°C | Max operating: 70°C
🏭
Industrial: ΔT ≤ 20°C, ambient up to 55°C
Control panels, industrial drives, DIN-rail equipment. Ambient inside enclosures can reach 55°C. Design traces for ΔT = 15-20°C to keep peak temperature below 75°C. Use heavier copper (2oz) for power boards.
Target: ΔT = 15-20°C | Max operating: 85°C
🚘
Automotive: ΔT ≤ 30°C, ambient up to 85°C
Under-hood automotive electronics face 85°C+ ambient. Design trace temperature rise to ≤ 30°C keeping peak temperature below 125°C. AEC-Q200 components rated accordingly. Use 2-3 oz copper and conservative derating.
Target: ΔT ≤ 30°C | Max operating: 125°C
✏
Telecom/Server: Continuous duty, IPC Class 3
24/7 operation at maximum rated current. Use IPC Class 3 standards. Design for ΔT = 10°C with 30% width margin. Verify with thermal simulation. Consider temperature monitoring in firmware.
Target: ΔT = 10°C | Safety factor: 1.3x width
⚡ Voltage Drop Budgets
📈
Power rails: ≤ 3% voltage drop
For VCC, VDD and main power distribution, keep total trace voltage drop under 3% of nominal voltage. At 3.3V this is only 99mV — a surprisingly tight budget for long traces. Factor in all traces in series: supply → connector → board → IC.
3.3V rail: max 99mV drop | 5V: max 150mV | 12V: max 360mV
💫
Analog/precision circuits: ≤ 1% drop
Op-amp supply rails, ADC reference voltages and precision analog supply traces must have voltage drop below 1% of the reference voltage. A 1mV drop on a 1.024V ADC reference causes 0.1% full-scale error.
ADC/DAC ref: max 0.5% | Precision amp supply: max 1%
②
Ground return paths are traces too
Ground traces carry the same current as supply traces but engineers often make them smaller. A 100mΩ ground trace creates the same voltage error as a 100mΩ supply trace. Size ground returns equally to supply traces. Better: use a ground plane.
For signal traces and logic below 30V, IPC-2221 allows 0.1mm conductor-to-conductor clearance. Most DRC rules default to 0.1-0.15mm. Always confirm with your PCB manufacturer's minimum capability.
≤30V uncoated: 0.1mm | Coated: 0.05mm
⚡
Mains voltage (230V AC): 1.5mm clearance
IEC 60950/62368 requires minimum 1.5mm clearance between mains conductors and 3.2mm between primary and secondary on uncoated boards. Creepage (surface distance) requirements are even larger — typically 6mm for 230V in pollution degree 2.
230V clearance: 1.5mm | Creepage: 6mm min (PD2)
⚠
High voltage DC (400-800V): 4-8mm clearance
EV battery voltages (400V, 800V) require large clearances. IEC 62368-1 requires 4mm for 400V, 6mm+ for 800V. Creepage depends on CTI (Comparative Tracking Index) of PCB material. FR4 (CTI 175) requires more creepage than Rogers or polyimide materials.
400V DC: min 4mm clearance | 800V DC: min 6mm clearance
🔌 EMC Guidelines for Traces
🔅
3W rule: keep edge-to-edge spacing ≥ 3W
To prevent crosstalk between adjacent traces, maintain edge-to-edge spacing of at least 3 times the trace width (3W rule). This keeps mutual coupling below -20dB. For critical signals (clocks, RF), use 5W spacing or add ground guard traces between them.
Spacing ≥ 3 x trace width for -20dB crosstalk
🔄
Return path rule: current follows the path of least impedance
At DC, return current flows through the shortest path. At high frequency, it flows directly beneath the signal trace. Slots or gaps in the ground plane force return current to detour, creating a large loop antenna. Never cut across a ground plane under a high-speed trace.
Keep ground plane continuous under all switching traces
②
Star grounding for mixed-signal boards
Connect digital ground and analog ground at a single star point near the power supply. This prevents digital switching noise from coupling into analog ground. Separate the planes physically and join only at one point — typically at the ADC or DAC GND pin or at the regulator.
Single GND connection point between AGND and DGND planes
These are the insights that experienced PCB designers know but are rarely documented. Some correct common misconceptions, some prevent costly respins.
TRICK 01 / MYTH
Two parallel traces do NOT give 2x current capacity
The IPC formula assumes a single trace in open air. Two parallel traces heat each other through mutual radiation. The actual current multiplier for 2 parallel traces of width W is approximately 1.76x, not 2x. For 3 parallel traces: ~2.3x, not 3x. If you need exactly 2x current, use a single trace of 1.8x width — it is more efficient and takes less board space.
Common Myth
TRICK 02 / GOTCHA
Via plating is always thinner than trace copper — vias are the real bottleneck
A 1 oz board has 35um of trace copper. But via barrel plating is typically only 18-25um (IPC Class 2: 20um minimum). This means a via is almost always the bottleneck for current carrying, not the trace. A 0.3mm drill via with 25um plating carries ~0.5A safely. Engineers frequently overestimate via current capacity. Always calculate via capacity separately from trace capacity.
Costly Gotcha
TRICK 03 / PRO TIP
Copper pour is not free — it creates soldering and reliability problems if done wrong
Solid copper pour floods create large thermal mass — great for heat spreading, terrible for hand soldering and rework. Always add thermal relief spokes (4-spoke cross) when connecting through-hole pins or vias to a copper pour. Without thermal relief, heat flows away before the solder joint reaches temperature, creating cold joints. Exception: SMD pads on power ICs benefit from direct thermal connection to the pour.
Pro Tip
TRICK 04 / GOTCHA
Acid traps — the silent killer of PCB trace reliability
Sharp inside corners (less than 90 degrees) create acid traps during wet etching — etchant gets trapped in the corner and keeps etching after the rest of the board is done. This thins the copper exactly where you least want it (at bends carrying current). The fix is always 45-degree chamfers or rounded corners. Modern DRC tools should flag acute inner angles. If yours does not, check manually on power traces.
Reliability Risk
TRICK 05 / PRO TIP
Kelvin sensing connections prevent measurement errors in power circuits
When measuring voltage across a current-sense resistor or a component, bring the voltage sense traces directly to the sense resistor pads using separate, thin traces. Never use the power carrying trace for voltage sensing — the resistance of the trace adds error to your measurement. This 4-wire (Kelvin) technique is standard in precision current sensing. The sense traces carry zero current and thus introduce zero voltage error. Critical for shunt resistors below 10 mohm.
Precision Tip
TRICK 06 / EMC
The 3W rule — keep trace edges 3 trace widths apart to prevent crosstalk
To keep crosstalk between adjacent traces below -20dB, maintain edge-to-edge spacing of at least 3 times the trace width (3W rule). Example: 0.15mm signal traces need 0.45mm edge-to-edge spacing (0.6mm center-to-center). Reducing to 2W spacing increases crosstalk to -14dB — significant for high-speed signals. For clock lines next to data lines, use 5W spacing or insert a ground guard trace between them.
EMC Rule
TRICK 07 / GOTCHA
Hatched ground planes for flexible PCBs — solid pours crack under flexing
For flexible PCBs (FPC) and rigid-flex boards, solid copper ground planes crack under repeated bending because copper work-hardens. Use a hatched (mesh) pattern — typically 0.1mm lines on a 0.5mm grid at 45 degrees. Hatched copper retains 60-70% of the conductivity of solid copper while allowing the board to flex without cracking. Specify the hatch pattern to your flex PCB manufacturer.
Flex PCB Specific
TRICK 08 / PRO TIP
Resistance increases 3.9% per 10 degC — this matters more than most engineers think
Copper resistance coefficient is 0.00393 per degC. A trace designed at 25 degC ambient will have 39% higher resistance if operating at 125 degC (automotive). This means a 100 mohm trace at room temp becomes 139 mohm at 125 degC — and voltage drop and power dissipation both increase. For automotive and industrial designs, always recalculate resistance at maximum operating temperature, not room temperature. Some designs that pass at 25 degC fail at 85 degC.